The present invention generally relates to digital signal processing systems and in particular to an arithmetic element controller for use in such systems that provides for address generation for three separate memories and for direct memory access of two of those memories from external devices.
The ability to perform sophisticated vector and scalar arithmetic operations in real time is a key requirement of signal processing systems. Often, however, this requirement is also accompanied by severe physical constraints upon the size, weight, power and cooling of the signal processing system. In the past, signal processor designers have had to compromise among competing requirements, many times resulting in processors with less than adequate performance.
Conventional signal processors may also be limited in performance due to relatively slow system clock rates of around five megahertz, and limited capability to operate on 16 bit fixed point data. The fixed point operational limitations of the conventional signal processor have become significant in many application environments. Many signal processing algorithms require arithmetic computations having a large dynamic range, making 32 bit floating point processing necessary.
The ability to network modular signal processors allows a system to efficiently meet a wide range of applications. Many signal processors are limited in their capability for networking.
With reference to the present invention, the implementation of hardware which efficiently provides for the generation of memory addresses for signal processor memories and for addresses which provides for direct memory access of data storage memories from external device is a key to efficient operation of a state of the art networkable signal processing system.